E-core CPU Design Manager

Job Details:

Job Description: 

We created the Intel Atom Processor (E-Core), a disruptive technology that enables a broad range of devices including entry PC's, smartphones, modems, 2 in 1 laptops, micro-servers, and other Internet-of-Things IoT devices. You will be part of a team, participating in the design of a future generation high performance Intel E-core microprocessor. You will work as a key member of a team participating in the design of E-core CPUs.

We are looking for a talented individual to manage a high performing team in the physical design of highly complex blocks from synthesis/APR through post-layout verification and tapeout.

This technical management position requires an engineer with broad synthesis APR design and verification experience and a strong desire to lead a team of experienced integration engineers.

The Responsibilities for this position will include but not be limited to:

• Manage a team of design engineers responsible for RTL to GDS activities.
• Plan, allocate resources, assign tasks and direct activities of the team to meet aggressive schedules and achieve milestone criteria.
  Identify and analyse progress gating issues and implement plans, tasks, and provide quick solutions.
• Propose creative, innovative methodology and process initiatives to consistently improve efficiency and quality of integration deliverables.
• Provide coaching, guidance and feedback to direct reports on career development, performance, and productivity issues.
• Build a strong and technically vital organization. Cultivate and reinforce appropriate group values, norms and behaviors.

Qualifications:

The successful candidate must possess a minimum of a BS or MS in Electrical Engineering or Computer Engineering with at least 10 years of hands on experience in this area and at least 3 years of experience in leading a team either as technical lead or as manager.

Additional qualifications include:

Hands-on experience in the following areas:

• Block floor planning, RTL to gate level netlist generation through synthesis, DFT insertion, placement, clock tree synthesis and route flows, power and static timing analysis and closure, validation of physical design including timing, electrical rules, DRC/LVS, noise, electromigration checks, formal equivalence verification.
• Successfully led one or more design tape-outs of complex, high performance, low-power CPUs.
• Able to provide technical leadership to a team of engineers involved in RTL to GDS APR build and verification flows.
• Able to provide technical guidance and support to team members throughout the project design cycle.
• Excellent verbal communication, technical presentation and leadership skills.
• Self-motivated and well organized.
• Candidate should be familiar with Synopsys or Cadence build tools.

Job Type:

Experienced Hire

Shift:

Shift 1 (Malaysia)

Primary Location: 

Malaysia, Penang

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Minimum of a BS or MS in Electrical Engineering or Computer Engineering with at least 10 years of hands-on experience in CPU design and at least 3 years in a leadership role (technical lead or manager). Required hands-on experience includes block floor planning, RTL to gate level netlist generation, DFT insertion, placement, clock tree synthesis and route flows, power and static timing analysis and closure, and validation of physical design (timing, electrical rules, DRC/LVS, noise, electromigration, formal equivalence verification). Must have successfully led one or more design tape-outs of complex, high-performance, low-power CPUs. Requires technical leadership, guidance, excellent verbal communication, technical presentation, and organizational skills. Familiarity with Synopsys or Cadence build tools is essential.