
// Open Role at Intel
Shape the future of graphics and compute technologies as a GPU Logic Design Engineer at Intel. Drive innovation in GPU IP designs, optimize for performance and power, and redefine user experiences for millions in a dynamic, collaborative environment.
As a GPU Logic Design Engineer at Intel, you will play a critical role in shaping the future of graphics and compute technologies. You will be part of a dynamic team driving innovation and delivering world-class GPU IP designs that power cutting-edge products worldwide. Your expertise will contribute directly to achieving Intel's performance, power, area, and quality goals.
This is an exciting opportunity to influence the definition and design of architecture and microarchitecture features, ensuring the seamless integration of GPU blocks into full chip designs. Your work will help redefine possibilities in graphics computation and enable extraordinary user experiences for millions.
Responsibilities will include but are not limited to:
Behavioral traits that we are looking for:
Note: This role requires regular onsite presence to fulfill essential job responsibilities.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum qualifications and are considered a plus factor in identifying top candidates.
Minimum Qualifications
Preferred Qualifications
Join us in shaping the future of technology by contributing to transformative innovations in GPU logic design. Apply today to unlock your potential and become part of our mission to create extraordinary solutions for the modern world.
Experienced Hire
Shift 1 (United States of America)
US, California, Folsom
US, California, Santa Clara
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
N/A
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel (https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003).
Annual Salary Range for jobs which could be performed in the US: $141,910.00-200,340.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
Bachelor’s degree in Electrical or Computer Engineering (or related field) with 4 years of industry experience, OR a Master’s degree with 3 years, OR a PhD with 1 year. Must have experience in RTL design & SystemVerilog coding, defining architecture specs and converting them into low-level designs, and GPU or CPU architecture experience.