Staff Logic Design Engineer

Job Details:

Job Description: 

Devices Development Group Malaysia (DDG-MYS) Client SoC Team is seeking highly motivated engineering talent to join Intel’s next-generation Client SoC development team as a SoC RTL/Logic Staff Design Engineer. In this role, you will contribute to Intel’s latest Client product families, helping build world-changing technology that reaches people around the globe.

Key Responsibilities

• Own DDG internal IP RTL design and development or integrate high-performance and high-bandwidth IP into Client SoC platforms.
• Define, implement, and deliver new IP features, change requests, and feature enhancements.
• Drive IP-to-SoC handoff quality, ensuring design completeness, compliance, and readiness for downstream integration.
• Perform logic and RTL integration into SoC, including power intent definition, signal handling across power planes and clock domains, and delivery of front-end collateral for system and software integration.
• Develop design solutions and collaborate closely with verification teams to validate functionality, features, and integration readiness.
• Execute front-end quality checks across RTL static analysis, synthesizability, timing and power convergence, netlist quality, formal equivalence verification, and related design quality milestones.

Qualifications:

• Bachelor or Master Degree in Electrical and Electronic Engineering, Computer Engineering, Computer Science, or a related discipline, with at least 3 years of experience in IP or SoC RTL/Logic Design.
• Strong knowledge of one or more of the following areas:
  • IP/subsystem architecture, I/O architecture, and industry-standard high-speed bus protocols.
  • SoC/ASIC design methodology and industry-standard front-end development practices.
  • SoC fabric and interconnect design.
  • RTL design using Verilog and System Verilog.
  • Industry front-end and RTL tools, flows, and design methodologies.
  • Experience using AI tools or AI-assisted engineering workflows to improve RTL/Logic development productivity, including design exploration, code generation, review, debug, documentation, and front-end quality checks.
  • Ability to orchestrate efficient development workflows by combining domain expertise, automation, scripting, AI-assisted tools, and structured engineering practices to accelerate delivery while maintaining design quality.
  • Pre-silicon or post-silicon lab debug and power-on experience.
  • Excellent communication, collaboration, problem-solving, and teamwork skills.

Job Type:

Experienced Hire

Shift:

Shift 1 (Malaysia)

Primary Location: 

Malaysia, Penang

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Bachelor or Master Degree in Electrical/Electronic Engineering, Computer Engineering, Computer Science, or related discipline with at least 3 years of experience in IP or SoC RTL/Logic Design. Strong knowledge of IP/subsystem architecture, SoC/ASIC design methodology, SoC fabric, RTL design using Verilog/System Verilog, industry front-end tools, and AI-assisted engineering workflows. Experience with pre-silicon or post-silicon lab debug is a plus. Excellent communication, collaboration, problem-solving, and teamwork skills are essential.