Active
full-time
Corporate Memory Organization
Job Summary
Join Intel as a Graduate Talent Memory Layout Design Engineer in Penang, Malaysia, and contribute to cutting-edge memory circuit design. This hybrid role offers a unique opportunity to master advanced layout tools and verification techniques within a fast-paced, technically challenging environment.
About this job
This role is for a Graduate Talent Memory Layout Design Engineer within Intel's Corporate Memory Organization. The engineer will be responsible for creating custom physical layouts for memory circuits using advanced CMOS technology, mastering Virtuoso XL for design and validation, and executing comprehensive DRC-LVS verification. The position focuses on developing optimized layout floorplans and maintaining high standards for design integrity.
Requirements
- You must possess a Bachelor's degree in Electronic/Microelectronic Engineering, Computer Engineering, or a related engineering discipline.
- Basic programming skills (UNIX shell scripting, Tcl, Perl).
- Familiar with DRC, LVS, and RV verification and debugging.
Benefits & Perks
- Eligible for our hybrid work model, allowing split time between on-site and off-site work.
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