Untitled Position

- Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science - 4+ years of experience in RTL design and implementation for ASIC/SoC development - Proficiency in Verilog/System Verilog for RTL coding and design - Experience with synthesis tools and timing closure methodologies - Understanding of clock domain crossings, power optimization, and timing closure (Preferred) - Exposure to SoC system integration and CPU subsystem design (Preferred) - Familiarity with standard bus protocols (AXI, AHB, etc.) and embedded processor architectures (Preferred) - Knowledge of high-speed and low-power design techniques (Preferred) - Experience with static timing analysis (STA) tools and methodologies (Preferred) - Hands-on experience with formal verification tools and techniques (Preferred) - Basic scripting skills (Python, TCL, etc.) for automation (Preferred) - Experience with EDA tools: HDL simulators (VCS, Questa, IES), lint tools (Spyglass), and FPGA prototyping tools (Preferred) - Ability to work in a dynamic environment and adapt to changing requirements (Preferred) - Strong problem-solving skills, collaborative mindset, and eagerness to learn (Preferred)