Untitled Position

- US Citizenship required - Ability to obtain US Government Security Clearance - Bachelor's degree in Electrical Engineering, Computer Engineering, or STEM-related field - 3+ years of experience with advanced CMOS processes (22nm and below) - 3+ years of combined experience in implementing ASIC DFT/DFM insertion (MBIST, LBIST, SCAN, JTAG) at both ASIC design block level and full chip level, including ATPG validation and DFT timing/signoff at SOC level - 2+ years of experience in one or more scripting languages (Python, Perl, Tcl, and/or shell scripting) - Strong customer-oriented attitude, self-motivation, collaborative, analytical problem-solving, and effective communication skills - Preferred: Active US Government Security Clearance with a minimum of Secret Level - Preferred: Post-graduate degree in Electrical/Computer Engineering or STEM-related field - Preferred: Hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration, Design Signoff, LVS, DRC, DFX/DFM, Reliability) - Preferred: Proficiency with major EDA tools for MBIST insertion, hierarchical SCAN and JTAG insertion, DFT constraint generation and ATPG validation for single die and multi-die designs - Preferred: Experience building/developing quality DFT/DFX insertion flow and ATPG validation flow - Preferred: Customer-facing experience in technical roles - Preferred: Experience with state-of-the-art process technology (7nm and below) and PDK-based technology evaluation