Senior DFT Logic Design Engineer

Job Details:

Job Description: 

About the Group

Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of an industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain.

Intel Foundry will be differentiated from other foundries with a combination of leading-edge packaging and process technology, committed capacity in the US and Europe, and a world-class IP portfolio that customers can choose from, including x86 cores, graphics, media, display, AI, interconnect, fabric and other critical foundational IP's, along with Arm and RISC-V ecosystem IP's. Foundry Services will also provide access to silicon design services to help our customers seamlessly turn silicon into solutions, using industry standard design packages. Come join us and do something wonderful.

The Aerospace, Defense, Government (ADG) - The Senior DFT Logic Design Engineer provides technical support to Intel Foundry Services customers on our PDKs, DFT/DFM insertion, ATPG validation methodology and flows.

The successful candidate will:

• Collaborate with internal teams across Intel and external stakeholders such as foundry customers' design teams, IP providers, and EDA vendors on issue resolution.
• Create content, application notes and deliver technical training/presentations.
• Drive quality of ASIC DFT/DFM and ATPG validation methodology, capability/flow and documentation for block level and SOC level.
• Support and provide Tool/Flow/Methodology on customer issues and challenges for successful customer tape-outs, and to increase customer satisfaction.

Core Competencies

• Customer-oriented attitude and mindset.
• Self-driven and results-oriented, capable of effectively working multiple tasks.
• Team player - effective team-work skillset to drive and find solutions for customer design implementation issues/challenges.
• Analytical problem-solving skills.
• Effective communication skills, as well as experience in collaboration, listening and providing feedback.

Qualifications:

The Minimum qualifications are required to be initially considered for this position.  Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• US Citizenship required.
• Ability to obtain a US Government Security Clearance.
• Bachelor's degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study.
• 3+ years of experience with advanced CMOS processes (16nm and below).
• 3+ years of experience in implementing ASIC DFT/DFM insertion (MBIST, LBIST, SCAN, JTAG, ...) at ASIC design block level and at full chip level. Performing ATPG validation and DFT timing and DFT signoff at SOC level.
• 4+ years of experience in one or more of the following scripting languages e.g. Python, Perl, Tcl, and/or shell scripting.
   

Preferred Qualifications

• Active US Government Security Clearance with a minimum of Secret level.
•  Post Graduate degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study.
• Hands-on experience in one or more areas of Design Implementation and methodology - (ASIC design, Fullchip Integration, Design Signoff, LVS, DRC, DFX/DFM, Reliability, etc).
•  Experience using major EDA tools suites for MBIST insertion, hierarchical SCAN and JTAG insertion, DFT constraint generation and ATPG validation for single die and multi-die design.
• Experience in building/developing quality DFT/DFX insertion flow and ATPG validation flow.
• Experience in working with RTL and Hard IP designers on DFT/DFM implementation methodology.
• Experience in working with physical designers on DFT/DFM physical implementation, validation, and DFT timing signoff.
• Experience with providing technical direction to engineering teams, including but not limited to customer support, driving methodologies to streamline design work
• Customer facing experience.
• Semiconductor foundry experience.

What We Offer

• Opportunity to work with cutting-edge DFT technologies for aerospace, defense, and government applications
• Direct customer engagement and technical leadership in advanced semiconductor design
• Access to Intel's most advanced foundry technologies and comprehensive EDA tool suites
• Competitive compensation
• Professional development in DFT methodologies and foundry services
• Direct impact on national security through advanced semiconductor technology solutions

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, Arizona, Phoenix

Additional Locations:

US, California, Santa Clara, US, Oregon, Hillsboro

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

US Citizenship required; ability to obtain a US Government Security Clearance; Bachelor's degree in Electrical/Computer Engineering, Computer Science, or STEM field; 3+ years of experience with advanced CMOS processes (16nm and below); 3+ years of experience in implementing ASIC DFT/DFM insertion (MBIST, LBIST, SCAN, JTAG) at block and full chip levels; 3+ years of experience performing ATPG validation and DFT timing/signoff at SOC level; 4+ years of experience in scripting languages (Python, Perl, Tcl, Shell). Preferred: Active US Government Security Clearance (Secret level); Post Graduate degree in Electrical/Computer Engineering, Computer Science, or STEM field; hands-on experience in Design Implementation and methodology (ASIC design, Fullchip Integration, Design Signoff, LVS, DRC, DFX/DFM, Reliability); experience using major EDA tool suites for MBIST, hierarchical SCAN, JTAG insertion, DFT constraint generation, and ATPG validation for single/multi-die design; experience in building/developing quality DFT/DFX insertion and ATPG validation flows; experience collaborating with RTL and Hard IP designers on DFT/DFM implementation methodology; experience collaborating with physical designers on DFT/DFM physical implementation, validation, and DFT timing signoff; experience providing technical direction to engineering teams; customer facing experience; semiconductor foundry experience.