// Open Role at Intel
Join Intel Foundry's DTP organization to drive next-generation semiconductor technology, focusing on custom layout methodologies, full-chip physical integration, and tapeout for advanced silicon designs. This role is perfect for engineers passionate about solving complex physical integration challenges at the cutting edge of process technology.
About the Role
Join the Design Technology Platform (DTP) organization within Intel Foundry and help drive the development of the methodologies, physical layouts, and silicon platforms that enable next-generation semiconductor technologies.
As a member of the X-Chip Full-Chip Integration team, you will play a key role in developing custom layout methodologies, leading full-chip physical integration, and driving physical verification and tapeout execution for advanced testchip and silicon lead vehicles on cutting-edge process technologies.
This role is ideal for engineers who have a passion for custom layout design, advanced-node physical design methodologies, and solving complex physical integration challenges. You will work at the intersection of technology development, physical design, verification, and manufacturing, collaborating with experts across Intel Foundry to enable future process technologies and silicon solutions.
What You'll Do
Responsibilities include, but are not limited to:
Successful Candidates Will Demonstrate
Why Join Intel Foundry?
At Intel Foundry, you'll have the opportunity to influence the future of semiconductor technology by helping develop the methodologies and silicon platforms that enable next-generation manufacturing processes.
In this role, you will:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications and Experience:
Masters' degree in Electrical Engineering, Computer Engineering, or a related field with 4+ years of industry experience. OR a PhD’s degree in the same filed with 1+ years of industry experience.
Your experience outlined above must be in the following:
Preferred Qualifications and Experience:
Location:
Primary – Hillsboro OR
Additional – Chandler AZ, Austin TX.
Experienced Hire
Shift 1 (United States of America)
US, Oregon, Hillsboro
US, Arizona, Phoenix, US, Texas, Austin
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
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We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.
Master's degree in Electrical Engineering, Computer Engineering, or related field with 4+ years of industry experience OR PhD with 1+ years. Experience in custom/analog/mixed-signal layout design at advanced nodes, front-end (FEOL) layout rules, transistor-level matching, parasitic layout concepts, custom silicon structures, and debugging physical verification (LVS, DRC, DFM) issues. Proficiency in Tcl, Python, or SKILL for automation. Experience with top-level floorplanning, RDL/bump planning, backside power delivery, and collaborating with PDK/Technology Development teams is a plus.